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SLVS631B – DECEMBER 2005 – REVISED SEPTEMBER 2009
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
DRVH
DRVH (with respect to LL)
Output voltage range
LL
PGOOD, DRVL
PGND
Operating free-air temperature, T
A
–0.8
–0.1
–0.8
–0.1
–0.1
–40
MAX
34
5.5
28
5.5
0.1
85
°C
V
UNIT
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
I
V5FILTPWM
I
V5FILTSKIP
I
V5DRVSDN
I
V5FILTSDN
V
OUT
V
VFB
V
VFB_TOL
I
VFB
R
Dischg
T
ONN
T
ONF
T
ONS
T
ON(MIN)
T
OFF(MIN)
T
SS
Supply current
Supply current
V5DRV shutdown current
V5FILT shutdown current
Output voltage
VFB regulation voltage
T
A
= 25°C, bandgap initial accuracy
VFB regulation voltage
tolerance
VFB input current
VOUT discharge resistance
Nominal on time
Fast on time
Slow on time
Minimum on time
Minimum off time
Internal soft start time
T
A
= 0°C to 85°C
T
A
= -40°C to 85°C
V
FB
= 0.75 V, absolute value
EN_PSV = 0 V, V
OUT
= 0.5 V
V
LL
= 12 V, V
OUT
= 2.5 V, R
TON
= 250 kΩ
V
LL
= 12 V, V
OUT
= 2.5 V, R
TON
= 100 kΩ
V
LL
= 12 V, V
OUT
= 2.5 V, R
TON
= 400 kΩ
V
OUT
= 0.75 V, R
TON
= 100 kΩ to 28 V
V
FB
= 0.7 V, LL = -0.1 V,
TRIP = open
Time from EN_PSV > 3 V to V
FB
regulation
value = 0.735 V
Source, V
VBST-DRVH
= 0.5 V
Sink, V
DRVH-LL
= 0.5 V
Source, V
V5DRV-DRVL
= 0.5 V
Sink, V
DRVL-PGND
= 0.5 V
DRVH-low (DRVH = 1 V) to DRVL-high
(DRVL = 4 V), LL = –0.05 V
DRVL-low (DRVL = 1 V) to DRVH-high
(DRVH = 4V), LL = –0.05 V
10
30
0.82
(1)
TEST CONDITIONS
V5FILT + V5DRV current, PWM, EN_PSV = float, VFB
= 0.77V, LL = –0.1 V
V5FILT + V5DRV current, auto-skip, EN_PSV = 5 V,
VFB = 0.77V, LL = 0.5 V
V5DRV current, EN_PSV = 0 V
V5FILT current, EN_PSV = 0 V
Adjustable output range
MIN
TYP
MAX
UNIT
400
250
0
4.5
0.75
750
–0.9%
–1.3%
–1.6%
0.02
20
750
264
80
330
1169
110
440
1.2
750
470
1
7.5
5.5
0.9%
1.3%
1.6%
0.1
32
μA
μA
μA
μA
V
mV
VOUT AND VFB VOLTAGES
μA
Ω
ns
ON-TIME TIMER AND INTERNAL SOFT START
396
140
ns
ns
ns
ns
1.5
ms
OUTPUT DRIVERS
R
DRVH
R
DRVL
DRVH resistance
DRVL resistance
5
1.5
5
1.5
20
40
7
2.5
7
2.5
50
60
Ω
Ω
Ω
Ω
ns
ns
T
D
Dead time
(1)
Design constraint, ensure actual on-time is larger than the max value (i.e., design R
TON
such that the min tolerance is 100 kΩ).
Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS51117
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