TPS3808
www.ti.com
SBVS050E – MAY 2004 – REVISED OCTOBER 2005
DEVICE OPERATION
The TPS3808 microprocessor supervisory product
family is designed to assert a RESET signal when
either the SENSE pin voltage drops below V
IT
or the
manual reset (MR) is driven low. The RESET output
remains asserted for a user-adjustable time after both
the manual reset (MR) and SENSE voltages return
above their thresholds. A broad range of voltage
threshold and reset delay time adjustments are
available, allowing these devices to be used in a wide
array of applications. Reset threshold voltages can be
factory-set from 0.82V to 3.3V or from 4.4V to 5.0V,
while the TPS3808G01 can be set to any voltage
above 0.405V using an external resistor divider. Two
preset delay times are also user-selectable:
connecting the C
T
pin to V
DD
results in a 300ms reset
delay, while leaving the C
T
pin open yields a 20ms
reset delay. In addition, connecting a capacitor
between C
T
and GND allows the designer to select
any reset delay period from 1.25ms to 10s.
supply line can be used to allow the reset signal for
the microprocessor to have a voltage higher than V
DD
(up to 6.5V). The pull-up resistor should be no
smaller than 10kΩ as a result of the finite impedance
of the RESET line.
SENSE INPUT
The SENSE input provides a terminal at which any
system voltage can be monitored. If the voltage on
this pin drops below V
IT
, then RESET is asserted.
The comparator has a built-in hysteresis to ensure
smooth RESET assertions and de-assertions. It is
good analog design practice to put a 1nF to 10nF
bypass capacitor on the SENSE input to reduce
sensitivity to transients and layout parasitics.
The TPS3808G01 can be used to monitor any
voltage rail down to 0.405V using the circuit shown in
V
IN
V
DD
R
1
TPS3808G01
SENSE
RESET
1nF
R
2
GND
V
OUT
V
IT
′
= (1 +
R
1
)0.405
R
2
RESET OUTPUT
A typical application of the TPS3808G25 used with
the OMAP1510 processor is shown in
The
open drain RESET output is typically connected to
the RESET input of a microprocessor. A pull-up
resistor must be used to hold this line high when
RESET is not asserted. The RESET output is
undefined for voltage below 0.8V, but this is normally
not a problem since most microprocessors do not
function below this voltage. RESET remains high
(unasserted) as long as SENSE is above its threshold
(V
IT
) and the manual reset (MR) is logic high. If either
SENSE falls below V
IT
or MR is driven low, RESET is
asserted, driving the RESET pin to a low impedance.
2.5V
SENSE V
DD
T PS 380 8G 25
MR
C
T
1M
Ω
V
DDSHV 1, 3, 6, 7, 9
O M AP 1510
Figure 11. Using the TPS3808G01 to Monitor a
User-Defined Threshold Voltage
MANUAL RESET (MR) INPUT
The manual reset (MR) input allows a processor or
other logic circuits to initiate a reset. A logic low
(0.3V
DD
) on MR causes RESET to assert. After MR
returns to a logic high and SENSE is above its reset
threshold, RESET is de-asserted after the user
defined reset delay expires. Note that MR is internally
tied to V
DD
using a 90kΩ resistor so this pin can be
left unconnected if MR will not be used.
See
for how MR can be used to monitor
multiple system voltages. Note that if the logic signal
driving MR does not go fully to V
DD
, there will be
some additional current draw into V
DD
as a result of
the internal pull-up resistor on MR. To minimize
current draw, a logic-level FET can be used as
illustrated in
RESET
GND
RESPWRON
GND
Figure 10. Typical Application of the TPS3808
with an OMAP Processor
Once MR is again logic high and SENSE is above V
IT
+ V
HYS
(the threshold hysteresis), a delay circuit is
enabled which holds RESET low for a specified reset
delay period. Once the reset delay has expired, the
RESET pin goes to a high impedance state. The
pull-up resistor from the open drain RESET to the
8
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