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SLVS590B – JULY 2005 – REVISED FEBRUARY 2008
(2)
RECOMMENDED OPERATING CONDITIONS
(1)
All voltage values are with respect to V
SS
unless otherwise noted.
MIN
V
DD
Input voltage range
Input voltage range
(3)
NOM
MAX
67
V
BIAS
16
1
2
2
2
20
UNIT
V
V
COM, SEN, SENP
FB, COMP, MODE, BL
AUX to COM
RSP to RSN
AUX
0
0
0
0
0
0
0
0.8
0.08
30
-40
-40
Sourcing current
Q
G
GATE loading
AUX load capacitance
V
BIAS
load capacitance
R
FREQ
T
J
T
A
(1)
(2)
(3)
V
BIAS
COMP
mA
nC
µF
µF
kΩ
°C
°C
25
1.5
300
125
85
Operating junction temperature range
Operating ambient temperature range
RSN, COM, and RTN should be tied together. SENP should be tied to V
DD
except for the buck configuration, where it should be tied to
the output positive rail.
TMR, FREQ, CLASS, DET, V
BIAS
, and GATE should not be externally driven.
Junction temperature may be a constraining factor for high bias power designs.
DISSIPATION RATINGS TABLE
PACKAGE
PWP (TSSOP-20)
(1)
(2)
(3)
(4)
(5)
θ
JP
°C/W
(1)
1.4
θ
JC
°C/W
26.62
θ
JA
°C/W
(2)
32.6
θ
JA
°C/W
(3)
151.9
θ
JA
°C/W
(4)
73.8
MAXIMUM POWER RATING
(W)
(5)
1.2
Thermal resistance junction to pad.
See TI document
for recommended layout. This is a best case, zero airflow number.
JEDEC method with low-k board (2 signal layers) and power pad not soldered (worst case).
JEDEC method with high-k board (4 layers, 2 signal and 2 planes) and power pad not soldered.
Based on TI recommended layout and 85°C ambient.
Copyright © 2005–2008, Texas Instruments Incorporated
3
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