SLVS590B – JULY 2005 – REVISED FEBRUARY 2008
www.ti.com
BLOCK DIAGRAM
FREQ
SENP
Translator
SEN
15 kW
V DD
REG.
UVLO
&
OVLO
COM
OSC.
CLK
ENABLE
AUX
15 kW
CE
REG.
V BIAS
HI
ERROR
AMP
1.5 V
LO
RUN
V BIAS
+
+
−
80 kW
−
−
+
PWM
COMP.
CLK
STATE
LATCH
D Q
R
EN ABLE
CE
GATE
DRIVER
GATE
COM
FB
COMP
0.27 V
MODE
50
m
A
CURRENT
LIMIT COMP
.
−
0.5 V
+
BL
CLK
DELA
Y
RSP
FAUL
T
COMP.
0.5 V
TMR
SOFT
START
and
FAUL
T
CTL
5
m
A
20 kW
X4
CNTR.
CLK
0.75 V
RUN
RSN
CE
11.3 V and
9.3 V
VDD
+
−
Detect
DET
Thermal
shutdown
21.9 V
and
21.28 V
Class
High
+
−
OTSD
0 = Hot
CLASS
10 V
Regulator
RTN
SMPS
CE
OTSD
UVLO
20.5 V
and
18 V
RTN
−
1.5 V
and
12 V
−
39.3 V
and
30.5 V
+
+
RTN
+
−
OTSD
SMPS
UVLO
RTN
375
m
s
Current
limit
RTN
36 mV
UVLO
11.2 mV
1
+
0
−
OTSD
0.08
W
VSS
8
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s):