TPA3116D2
TPA3118D2
TPA3130D2
www.ti.com
SLOS708B –APRIL 2012–REVISED MAY 2012
GAIN SETTING AND MASTER / SLAVE
The gain of the TPA31xxD2 family is set by the voltage divider connected to the GAIN/SLV control pin. Master or
Slave mode is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four
stages sets the GAIN in Master mode in gains of 20, 26, 32, 36 dB respectively, while the next four stages sets
the GAIN in Slave mode in gains of 20, 26, 32, 36 dB respectively. The gain setting is latched during power-up
and cannot be changed while device is powered. Table 1 shows the recommended resistor values and the state
and gain:
Table 1. GAIN and MASTER/SLAVE
MASTER / SLAVE
GAIN
R1 (to GND)(1)
R2 (to GVDD)(1)
INPUT IMPEDANCE
MODE
Master
Master
Master
Master
Slave
20 dB
26 dB
32 dB
36 dB
20 dB
26 dB
32 dB
36 dB
5.6 kΩ
20 kΩ
39 kΩ
47 kΩ
51 kΩ
75 kΩ
100 kΩ
100 kΩ
OPEN
100 kΩ
100 kΩ
75 kΩ
51 kΩ
47 kΩ
39 kΩ
16 kΩ
60 kΩ
30 kΩ
15 kΩ
9 kΩ
60 kΩ
30 kΩ
15 kΩ
9 kΩ
Slave
Slave
Slave
(1) Resistor tolerance should be 5% or better.
5
6
INNR
2
1
PLIMIT
GVDD
1
C5 1 µF
2
7
2
1
R2
8
51 k
GAIN/SLV
GND
9
R1 51 k
10
In Master mode, SYNC terminal is an output, in Slave mode, SYNC terminal is an input for a clock input. TTL
logic levels with compliance to GVDD.
INPUT IMPEDANCE
The TPA31xxD2 family input stage is a fully differential input stage and the input impedance changes with the
gain setting from 9 kΩ at 36 dB gain to 60 kΩ at 20 dB gain. Table 1 lists the values from min to max gain. The
tolerance of the input resistor value is ±20% so the minimum value will be higher than 7.2 kΩ. The inputs need to
be AC-coupled to minimize the output dc-offset and ensure correct ramping of the output voltages during power-
ON and power-OFF. The input ac-coupling capacitor together with the input impedance forms a high-pass filter
with the following cut-off frequency:
1
ƒ
f =
2pZiCi
(1)
If a flat bass response is required down to 20 Hz the recommended cut-off frequency is a tenth of that, 2 Hz.
Table 2 lists the recommended ac-couplings capacitors for each gain step. If a -3 dB is accepted at 20 Hz 10
times lower capacitors can used – for example, a 1 µF can be used.
Table 2. Recommended Input AC-Coupling Capacitors
GAIN
20 dB
26 dB
32 dB
36 dB
INPUT IMPEDANCE
INPUT CAPACITANCE
HIGH-PASS FILTER
1.8 Hz
60 kΩ
30 kΩ
15 kΩ
9 kΩ
1.5 µF
3.3 µF
5.6 µF
10 µF
1.6 Hz
2.3 Hz
1.8 Hz
Copyright © 2012, Texas Instruments Incorporated
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