TPA2012D2
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SLOS438C–DECEMBER 2004–REVISED MARCH 2007
BOARD LAYOUT
In making the pad size for the WCSP balls, it is recommended that the layout use nonsolder mask defined
(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the
opening size is defined by the copper pad width. Figure 36 and Table 2 shows the appropriate diameters for a
WCSP layout. The TPA2012D2 evaluation module (EVM) layout is shown in the next section as a layout
example.
Copper
Trace Width
Solder
Pad Width
Solder Mask
Opening
Copper Trace
Thickness
Solder Mask
Thickness
Figure 36. Land Pattern Dimensions
Table 2. Land Pattern Dimensions(1)(2)(3)(4)
(5)
(6)(7)
SOLDER PAD
DEFINITIONS
COPPER
PAD
SOLDER MASK
OPENING
COPPER
THICKNESS
STENCIL
STENCIL
THICKNESS
OPENING
Nonsolder mask
defined (NSMD)
275 µm
(+0.0, -25 µm)
275 µm x 275 µm Sq.
(rounded corners)
375 µm (+0.0, -25 µm)
1 oz max (32 µm)
125 µm thick
(1) Circuit traces from NSMD defined PWB lands should be 75 µm to 100 µm wide in the exposed area inside the solder mask opening.
Wider trace widths reduce device stand off and impact reliability.
(2) Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the
intended application.
(3) Recommend solder paste is Type 3 or Type 4.
(4) For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance.
(5) Solder mask thickness should be less than 20 µm on top of the copper circuit pattern
(6) Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in
inferior solder paste volume control.
(7) Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional component movement due to
solder wetting forces.
Component Location
Place all the external components very close to the TPA2012D2. Placing the decoupling capacitor, CS, close to
the TPA2012D2 is important for the efficiency of the Class-D amplifier. Any resistance or inductance in the trace
between the device and the capacitor can cause a loss in efficiency.
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