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TMS570LS3137 参数 Datasheet PDF下载

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型号: TMS570LS3137
PDF下载: 下载PDF文件 查看货源
内容描述: TMS570LS3137 16位/ 32位RISC闪存微控制器 [TMS570LS3137 16/32-Bit RISC Flash Microcontroller]
分类和应用: 闪存微控制器
文件页数/大小: 159 页 / 2834 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS570LS3137  
SPNS162.SEPTEMBER 2011  
www.ti.com  
4.3.2 Power-Down Sequence  
The different supplies to the device can be powered down in any order.  
4.3.3 Power-On Reset: nPORRST  
This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core  
supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an  
internal pulldown.  
4.3.3.1 nPORRST Electrical and Timing Requirements  
Table 4-4. Electrical Requirements for nPORRST  
NO Parameter  
MIN  
MAX  
Unit  
VCCPORL  
VCC low supply level when nPORRST must be active during  
power-up  
0.5  
V
VCCPORH  
VCC high supply level when nPORRST must remain active during  
power-up and become active during power down  
1.14  
V
V
V
VCCIOPORL  
VCCIOPORH  
VIL(PORRST)  
VCCIO / VCCP low supply level when nPORRST must be active during  
power-up  
1.1  
VCCIO / VCCP high supply level when nPORRST must remain active  
during power-up and become active during power down  
3.0  
Low-level input voltage of nPORRST VCCIO > 2.5V  
Low-level input voltage of nPORRST VCCIO < 2.5V  
0.2 * VCCIO  
0.5  
V
V
3
tsu(PORRST)  
Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL  
0
ms  
during power-up  
6
7
th(PORRST)  
tsu(PORRST)  
Hold time, nPORRST active after VCC > VCCPORH  
1
2
ms  
Setup time, nPORRST active before VCC < VCCPORH during power  
µs  
down  
8
9
th(PORRST)  
th(PORRST)  
tf(nPORRST)  
Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH  
Hold time, nPORRST active after VCC < VCCPORL  
1
0
ms  
ms  
ns  
500  
2000  
Filter time nPORRST pin;  
pulses less than MIN will be filtered out, pulses greater than MAX  
will generate a reset.  
3.3 V  
1.2 V  
VCCIOPORH  
VCCIOPORH  
VCCIO / VCCP  
8
6
VCCPORH  
VCC  
VCCPORH  
7
6
VCCIOPORL  
7
VCCIOPORL  
VCCPORL  
VCCPORL  
VCC (1.2 V)  
VCCIO / VCCP(3.3 V)  
3
9
VIL  
VIL  
VIL  
VIL(PORRST)  
VIL(PORRST)  
nPORRST  
NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing.  
Figure 4-1. nPORRST Timing Diagram  
54  
System Information and Electrical Specifications  
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Copyright © 2011, Texas Instruments Incorporated  
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