TMS570LS3137
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SPNS162.–SEPTEMBER 2011
4.3 Power Sequencing and Power On Reset
4.3.1 Power-Up Sequence
There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The
power-up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see
Table 4-4 for more details), core voltage rising above the minimum core supply threshold and the release
of power-on reset. The high frequency oscillator will start up first and its amplitude will grow to an
acceptable level. The oscillator start up time is dependent on the type of oscillator and is provided by the
oscillator vendor. The different supplies to the device can be powered up in any order.
The device goes through the following sequential phases during power up.
Table 4-3. Power-Up Phases
Oscillator start-up and validity check
eFuse autoload
1032 oscillator cycles
1180 oscillator cycles
688 oscillator cycles
617 oscillator cycles
3517 oscillator cycles
Flash pump power-up
Flash bank power-up
Total
The CPU reset is released at the end of the above sequence and fetches the first instruction from address
0x00000000.
Copyright © 2011, Texas Instruments Incorporated
System Information and Electrical Specifications
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