TMS570LS3137
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SPNS162.–SEPTEMBER 2011
2.4.2.10 Multi-Buffered Serial Peripheral Interface Modules (MibSPI)
Table 2-32. ZWT Multi-Buffered Serial Peripheral Interface Modules (MibSPI)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
MIBSPI1CLK
F18
R2
I/O
Pull Up
Programmable, MibSPI1 clock, or GIO
20uA
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]
MIBSPI1NCS[1]/N2HET1[17]/MII_COL
MIBSPI1NCS[2]/N2HET1[19]/MDIO
MIBSPI1NCS[3]/N2HET1[21]
MibSPI1 chip select, or
GIO
F3
G3
J3
N2HET1[15]/MIBSPI1NCS[4]
N1
Pull Down Programmable, MibSPI1 chip select, or
20uA GIO
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]
MIBSPI1SIMO
P1
G19
F19
Pull Up
Programmable, MibSPI1 enable, or GIO
20uA
MibSPI1 slave-in
master-out, or GIO
N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]
E18
Pull Down Programmable, MibSPI1 slave-in
20uA master-out, or GIO
MIBSPI1SOMI
G18
R2
V9
Pull Up
Programmable, MibSPI1 slave-out
20uA master-in, or GIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]
MIBSPI3CLK
I/O
Pull Up
Programmable, MibSPI3 clock, or GIO
20uA
MIBSPI3NCS[0]/AD2EVT/GIOB[2]
MIBSPI3NCS[1]/N2HET1[25]/MDCLK
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]
V10
V5
MibSPI3 chip select, or
GIO
B2
C3
E3
Pull Up
Pull Up
Programmable, MibSPI3 chip select, or
20uA
GIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]
W9
Programmable, MibSPI3 chip select, or
20uA
GIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]
W9
W8
MibSPI3 enable, or GIO
MIBSPI3SIMO
MibSPI3 slave-in
master-out, or GIO
MIBSPI3SOMI
V8
MibSPI3 slave-out
master-in, or GIO
MIBSPI5CLK/DMM_DATA[4]/MII_TXEN
MIBSPI5NCS[0]/DMM_DATA[5]
H19
E19
B6
I/O
Pull Up
Programmable, MibSPI5 clock, or GIO
20uA
MibSPI5 chip select, or
GIO
MIBSPI5NCS[1]/DMM_DATA[6]
MIBSPI5NCS[2]/DMM_DATA[2]
W6
MIBSPI5NCS[3]/DMM_DATA[3]
T12
H18
J19
E16
H17
G17
J18
E17
H16
G16
MIBSPI5NENA/DMM_DATA[7]/MII_RXD[3]
MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]
MIBSPI5SIMO[1]/DMM_DATA[9]
MIBSPI5SIMO[2]/DMM_DATA[10]
MIBSPI5SIMO[3]/DMM_DATA[11]
MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]
MIBSPI5SOMI[1]/DMM_DATA[13]
MIBSPI5SOMI[2]/DMM_DATA[14]
MIBSPI5SOMI[3]/DMM_DATA[15]
MibSPI5 enable, or GIO
MibSPI5 slave-in
master-out, or GIO
Copyright © 2011, Texas Instruments Incorporated
Device Package and Terminal Functions
29
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