TMS320F2808PZA 参数 Datasheet PDF下载

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SPRS230M – OCTOBER 2003 – REVISED MARCH 2011

4.6.2

ADC Registers

The ADC operation is configured, controlled, and monitored by the registers listed in

Table 4-5. ADC Registers

(1)

NAME

ADDRESS

(1)

0x7100

0x7101

0x7102

0x7103

0x7104

0x7105

0x7106

0x7107

0x7108

0x7109

0x710A

0x710B

0x710C

0x710D

0x710E

0x710F

0x7110

0x7111

0x7112

0x7113

0x7114

0x7115

0x7116

0x7117

0x7118

0x7119

0x711A –

0x711B

0x711C

0x711D

0x711E –

0x711F

0x0B00

0x0B01

0x0B02

0x0B03

0x0B04

0x0B05

0x0B06

0x0B07

0x0B08

0x0B09

0x0B0A

0x0B0B

0x0B0C

0x0B0D

0x0B0E

0x0B0F

ADDRESS

(2)

SIZE (x16)

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

1

1

2

ADC Control Register 1

ADC Control Register 2

ADC Maximum Conversion Channels Register

ADC Channel Select Sequencing Control Register 1

ADC Channel Select Sequencing Control Register 2

ADC Channel Select Sequencing Control Register 3

ADC Channel Select Sequencing Control Register 4

ADC Auto-Sequence Status Register

ADC Conversion Result Buffer Register 0

ADC Conversion Result Buffer Register 1

ADC Conversion Result Buffer Register 2

ADC Conversion Result Buffer Register 3

ADC Conversion Result Buffer Register 4

ADC Conversion Result Buffer Register 5

ADC Conversion Result Buffer Register 6

ADC Conversion Result Buffer Register 7

ADC Conversion Result Buffer Register 8

ADC Conversion Result Buffer Register 9

ADC Conversion Result Buffer Register 10

ADC Conversion Result Buffer Register 11

ADC Conversion Result Buffer Register 12

ADC Conversion Result Buffer Register 13

ADC Conversion Result Buffer Register 14

ADC Conversion Result Buffer Register 15

ADC Control Register 3

ADC Status Register

Reserved

ADC Reference Select Register

ADC Offset Trim Register

Reserved

DESCRIPTION

ADCTRL1

ADCTRL2

ADCMAXCONV

ADCCHSELSEQ1

ADCCHSELSEQ2

ADCCHSELSEQ3

ADCCHSELSEQ4

ADCASEQSR

ADCRESULT0

ADCRESULT1

ADCRESULT2

ADCRESULT3

ADCRESULT4

ADCRESULT5

ADCRESULT6

ADCRESULT7

ADCRESULT8

ADCRESULT9

ADCRESULT10

ADCRESULT11

ADCRESULT12

ADCRESULT13

ADCRESULT14

ADCRESULT15

ADCTRL3

ADCST

Reserved

ADCREFSEL

ADCOFFTRIM

Reserved

(1)

(2)

The registers in this column are Peripheral Frame 2 Registers.

The ADC result registers are dual mapped in the 280x DSP. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait-states and left

justified. Locations in Peripheral frame 0 space (0x0B00-0x0B0F) are 0 wait sates and right justified. During high-speed/continuous

conversion use of the ADC, use the 0 wait-state locations for fast transfer of ADC results to user memory.

Copyright © 2003–2011, Texas Instruments Incorporated

Peripherals

67

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