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SPRS230M – OCTOBER 2003 – REVISED MARCH 2011
The wait-states for the various spaces in the memory map area are listed in
Table 3-6. Wait-states
AREA
M0 and M1 SARAMs
Peripheral Frame 0
Peripheral Frame 1
Peripheral Frame 2
L0 and L1 SARAMs
OTP
WAIT-STATES
0-wait
0-wait
0-wait (writes)
2-wait (reads)
0-wait (writes)
2-wait (reads)
0-wait
Programmed via the Flash registers. 1-wait-state operation
Programmable,
is possible at a reduced CPU frequency. See
1-wait minimum
for more information.
Programmed via the Flash registers. 0-wait-state operation
Programmable, is possible at reduced CPU frequency. The CSM password
0-wait minimum locations are hardwired for 16 wait-states. See
for more information.
0-wait
1-wait
Fixed
Fixed
COMMENTS
Fixed
Fixed
Fixed. The eCAN peripheral can extend a cycle as needed.
Back-to-back writes will introduce a 1-cycle delay.
Fixed
Flash
H0 SARAM
Boot-ROM
Copyright © 2003–2011, Texas Instruments Incorporated
Functional Overview
33
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