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TMS320F28232ZHHA 参数 Datasheet PDF下载

TMS320F28232ZHHA图片预览
型号: TMS320F28232ZHHA
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号控制器(DSC ) [Digital Signal Controllers (DSCs)]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置时钟
文件页数/大小: 195 页 / 2496 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F28335, TMS320F28334, TMS320F28332  
TMS320F28235, TMS320F28234, TMS320F28232  
www.ti.com  
SPRS439IJUNE 2007REVISED MARCH 2011  
6.14.6 External Interface Write Timing  
Table 6-40. External Interface Write Switching Characteristics  
PARAMETER  
MIN  
MAX  
1
UNIT  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
td(XCOH-XZCSL)  
td(XCOHL-XZCSH)  
td(XCOH-XA)  
Delay time, XCLKOUT high to zone chip-select active low  
Delay time, XCLKOUT high or low to zone chip-select inactive high  
Delay time, XCLKOUT high to address valid  
Delay time, XCLKOUT high/low to XWE0, XWE1 (1) low  
Delay time, XCLKOUT high/low to XWE0, XWE1 high  
Delay time, XCLKOUT high to XR/W low  
–1  
0.5  
1.5  
2
td(XCOHL-XWEL)  
td(XCOHL-XWEH)  
td(XCOH-XRNWL)  
td(XCOHL-XRNWH)  
ten(XD)XWEL  
2
1
Delay time, XCLKOUT high/low to XR/W high  
–1  
0
0.5  
Enable time, data bus driven from XWE0, XWE1 low  
Delay time, data valid after XWE0, XWE1 active low  
Hold time, address valid after zone chip-select inactive high  
Hold time, write data valid after XWE0, XWE1 inactive high  
Maximum time for DSP to release the data bus after XR/W inactive high  
td(XWEL-XD)  
1
(2)  
(3)  
th(XA)XZCSH  
th(XD)XWE  
TW – 2  
tdis(XD)XRNW  
4
(1) XWE1 is used in 32-bit data bus mode only. In 16-bit mode, this signal is XA0.  
(2) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which remains high.  
This includes alignment cycles.  
(3) TW = Trail period, write access. See Table 6-36.  
Copyright © 2007–2011, Texas Instruments Incorporated  
Electrical Specifications  
157  
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Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234  
TMS320F28232