TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
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SPRS439I–JUNE 2007–REVISED MARCH 2011
6.14.5 External Interface Read Timing
Table 6-38. External Interface Read Timing Requirements
MIN
MAX
UNIT
ns
(1)
ta(A)
Access time, read data from address valid
(LR + AR) – 16
(1)
ta(XRD)
Access time, read data valid from XRD active low
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
AR – 14
ns
tsu(XD)XRD
th(XD)XRD
14
0
ns
ns
(1) LR = Lead period, read access. AR = Active period, read access. See Table 6-36.
Table 6-39. External Interface Read Switching Characteristics
PARAMETER
MIN
MAX
1
UNIT
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
–1
0.5
1.5
0.5
0.5
ns
ns
td(XCOHL-XRDL)
td(XCOHL-XRDH)
th(XA)XZCSH
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
ns
–1.5
(1)
ns
ns
(1)
th(XA)XRD
ns
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
Copyright © 2007–2011, Texas Instruments Incorporated
Electrical Specifications
155
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