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TMS320F28232ZJZQ 参数 Datasheet PDF下载

TMS320F28232ZJZQ图片预览
型号: TMS320F28232ZJZQ
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号控制器(DSC ) [Digital Signal Controllers (DSCs)]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器时钟
文件页数/大小: 195 页 / 2496 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F28335, TMS320F28334, TMS320F28332  
TMS320F28235, TMS320F28234, TMS320F28232  
www.ti.com  
SPRS439IJUNE 2007REVISED MARCH 2011  
4.7.2 ADC Registers  
The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-6.  
Table 4-6. ADC Registers(1)  
NAME  
ADDRESS(1) ADDRESS(2) SIZE (x16)  
DESCRIPTION  
ADCTRL1  
0x7100  
0x7101  
0x7102  
0x7103  
0x7104  
0x7105  
0x7106  
0x7107  
0x7108  
0x7109  
0x710A  
0x710B  
0x710C  
0x710D  
0x710E  
0x710F  
0x7110  
0x7111  
0x7112  
0x7113  
0x7114  
0x7115  
0x7116  
0x7117  
0x7118  
0x7119  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ADC Control Register 1  
ADC Control Register 2  
ADCTRL2  
ADCMAXCONV  
ADCCHSELSEQ1  
ADCCHSELSEQ2  
ADCCHSELSEQ3  
ADCCHSELSEQ4  
ADCASEQSR  
ADCRESULT0  
ADCRESULT1  
ADCRESULT2  
ADCRESULT3  
ADCRESULT4  
ADCRESULT5  
ADCRESULT6  
ADCRESULT7  
ADCRESULT8  
ADCRESULT9  
ADCRESULT10  
ADCRESULT11  
ADCRESULT12  
ADCRESULT13  
ADCRESULT14  
ADCRESULT15  
ADCTRL3  
ADC Maximum Conversion Channels Register  
ADC Channel Select Sequencing Control Register 1  
ADC Channel Select Sequencing Control Register 2  
ADC Channel Select Sequencing Control Register 3  
ADC Channel Select Sequencing Control Register 4  
ADC Auto-Sequence Status Register  
0x0B00  
0x0B01  
0x0B02  
0x0B03  
0x0B04  
0x0B05  
0x0B06  
0x0B07  
0x0B08  
0x0B09  
0x0B0A  
0x0B0B  
0x0B0C  
0x0B0D  
0x0B0E  
0x0B0F  
ADC Conversion Result Buffer Register 0  
ADC Conversion Result Buffer Register 1  
ADC Conversion Result Buffer Register 2  
ADC Conversion Result Buffer Register 3  
ADC Conversion Result Buffer Register 4  
ADC Conversion Result Buffer Register 5  
ADC Conversion Result Buffer Register 6  
ADC Conversion Result Buffer Register 7  
ADC Conversion Result Buffer Register 8  
ADC Conversion Result Buffer Register 9  
ADC Conversion Result Buffer Register 10  
ADC Conversion Result Buffer Register 11  
ADC Conversion Result Buffer Register 12  
ADC Conversion Result Buffer Register 13  
ADC Conversion Result Buffer Register 14  
ADC Conversion Result Buffer Register 15  
ADC Control Register 3  
ADCST  
ADC Status Register  
0x711A –  
0x711B  
Reserved  
2
ADCREFSEL  
ADCOFFTRIM  
0x711C  
0x711D  
1
1
ADC Reference Select Register  
ADC Offset Trim Register  
0x711E –  
0x711F  
Reserved  
2
(1) The registers in this column are Peripheral Frame 2 Registers.  
(2) The ADC result registers are dual mapped. Locations in Peripheral Frame 2 (0x7108–0x7117) are 2 wait-states and left justified.  
Locations in Peripheral frame 0 space (0x0B00–0x0B0F) are 1 wait-state for CPU accesses and 0 wait state for DMA accesses and  
right justified. During high speed/continuous conversion use of the ADC, use the 0 wait-state locations for fast transfer of ADC results to  
user memory.  
Copyright © 2007–2011, Texas Instruments Incorporated  
Peripherals  
83  
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Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234  
TMS320F28232