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TMS320F28232ZJZQ 参数 Datasheet PDF下载

TMS320F28232ZJZQ图片预览
型号: TMS320F28232ZJZQ
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号控制器(DSC ) [Digital Signal Controllers (DSCs)]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器时钟
文件页数/大小: 195 页 / 2496 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F28335, TMS320F28334, TMS320F28332  
TMS320F28235, TMS320F28234, TMS320F28232  
www.ti.com  
SPRS439IJUNE 2007REVISED MARCH 2011  
SYSCLKOUT  
System  
Control Block  
High-Speed  
DSP  
Prescaler  
HALT  
HSPCLK  
ADCENCLK  
Analog  
MUX  
Result Registers  
70A8h  
Result Reg 0  
Result Reg 1  
ADCINA0  
S/H  
ADCINA7  
ADCINB0  
ADCINB7  
12-Bit  
ADC  
Module  
Result Reg 7  
Result Reg 8  
70AFh  
70B0h  
S/H  
Result Reg 15  
70B7h  
ADC Control Registers  
S/W  
S/W  
EPWMSOCB  
EPWMSOCA  
GPIO/  
SOC  
SOC  
Sequencer 2  
Sequencer 1  
XINT2_ADCSOC  
Figure 4-8. Block Diagram of the ADC Module  
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent  
possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths.  
This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs.  
Furthermore, proper isolation techniques must be used to isolate the ADC module power pins ( VDD1A18  
,
VDD2A18 , VDDA2, VDDAIO) from the digital supply.Figure 4-9 shows the ADC pin connections for the devices.  
NOTE  
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the  
ADC module is controlled by the high-speed peripheral clock (HSPCLK).  
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT  
signals is as follows:  
ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the  
clock to the register will still function. This is necessary to make sure all registers and  
modes go into their default reset state. The analog module, however, will be in a  
low-power inactive state. As soon as reset goes high, then the clock to the registers  
will be disabled. When the user sets the ADCENCLK signal high, then the clocks to  
the registers will be enabled and the analog module will be enabled. There will be a  
certain time delay (ms range) before the ADC is stable and can be used.  
HALT: This mode only affects the analog module. It does not affect the registers. In  
this mode, the ADC module goes into low-power mode. This mode also will stop the  
clock to the CPU, which will stop the HSPCLK; therefore, the ADC register logic will  
be turned off indirectly.  
Copyright © 2007–2011, Texas Instruments Incorporated  
Peripherals  
79  
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Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234  
TMS320F28232