TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com
SPRS439I–JUNE 2007–REVISED MARCH 2011
2.1 Pin Assignments
The 176-pin PGF/PTP low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2-1. The
179-ball ZHH ball grid array (BGA) terminal assignments are shown in Figure 2-2 through Figure 2-5. The
176-ball ZJZ plastic ball grid array (PBGA) terminal assignments are shown in Figure 2-6 through
Figure 2-9.Table 2-3 describes the function(s) of each pin.
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
GPIO76/XD3
GPIO77/XD2
GPIO78/XD1
GPIO79/XD0
88 GPIO48/ECAP5/XD31
87 TCK
86 EMU1
85
84
83
EMU0
V
DD3VFL
GPIO38/XWE0
XCLKOUT
V
SS
V
82 TEST2
81 TEST1
80
79 TMS
78
DD
CIRXDA/XZCS6
V
SS
XRS
GPIO28/SCIRXDA/XZCS6
GPIO34/ECAP1/XREADY
V
TRST
DDIO
V
77 TDO
76 TDI
SS
GPIO36/SCIRXDA/XZCS0
V
75 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
74 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
73 GPIO27/ECAP4/EQEP2S/MFSXB
72 GPIO26/ECAP3/EQEP2I/MCLKXB
DD
V
SS
GPIO35/SCITXDA/XR/W
XRD
GPIO37/ECAP2/XZCS7
GPIO40/XA0/XWE1
V
71
70
DDIO
V
SS
GPIO41/XA1
GPIO42/XA2
69 GPIO25/ECAP2/EQEP2B/MDRB
68 GPIO24/ECAP1/EQEP2A/MDXB
67 GPIO23/EQEP1I/MFSXA/SCIRXDB
66 GPIO22/EQEP1S/MCLKXA/SCITXDB
65 GPIO21/EQEP1B/MDRA/CANRXB
64 GPIO20/EQEP1A/MDXA/CANTXB
63 GPIO19/SPISTEA/SCIRXDB/CANTXA
62 GPIO18/SPICLKA/SCITXDB/CANRXA
V
V
DD
V
SS
GPIO43/XA3
GPIO44/XA4
GPIO45/XA5
V
DDIO
V
61
60
59
58
SS
GPIO46/XA6
GPIO47/XA7
DD
V
V
V
SS
DD2A18
SS2AGND
GPIO80/XA8 163
164
165
166
167
168
169
170
171
GPIO81/XA9
GPIO82/XA10
57 ADCRESEXT
56 ADCREFP
55 ADCREFM
54 ADCREFIN
53 ADCINB7
V
SS
V
DD
GPIO83/XA11
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
GPIO84/XA12
V
52
51
50
49
48
47
46
45
DDIO
V
SS
GPIO85/XA13 172
GPIO86/XA14
GPIO87/XA15
173
174
175
176
GPIO39/XA16
GPIO31/CANTXA/XA17
V
DDAIO
Figure 2-1. F2833x, F2823x 176-Pin PGF/PTP LQFP (Top View)
NOTE
The powerpad on the bottom side of the PTP package is not connected to the ground (GND)
of the die. Proper thermal management of the PowerPAD™ package requires PCB
preparation. A thermal land is required on the surface of the PCB directly underneath the
body of the PowerPAD package. The size of the thermal land should be as large as needed
to dissipate the required heat. Note that the PowerPAD package with exposed pad down
must be soldered to the PCB. Refer to the PowerPAD™ Thermally Enhanced Package
Application Report (literature number SLMA002) for more details on using the PowerPAD
package.
Copyright © 2007–2011, Texas Instruments Incorporated
Introduction
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