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SPRS439I – JUNE 2007 – REVISED MARCH 2011
Table 6-56. McBSP Switching Characteristics
(1)
NO.
M1
M2
M3
M4
M5
M6
M7
t
c(CKRX)
t
w(CKRXH)
t
w(CKRXL)
t
d(CKRH-FRV)
t
d(CKXH-FXV)
t
dis(CKXH-DXHZ)
t
d(CKXH-DXV)
PARAMETER
Cycle time, CLKR/X
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
Disable time, CLKX high to DX high impedance
following last data bit
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
Delay time, CLKX high to DX valid
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
M8
t
en(CKXH-DX)
Enable time, CLKX high to DX driven
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
M9
t
d(FXH-DXV)
Delay time, FSX high to DX valid
Only applies to first bit transmitted when
in Data Delay 0 (XDATDLY=00b) mode.
M10
t
en(FXH-DX)
Enable time, FSX high to DX driven
Only applies to first bit transmitted when
in Data Delay 0 (XDATDLY=00b) mode
(1)
(2)
(3)
DXENA = 0
DXENA = 1
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
DXENA = 0
DXENA = 1
CLKX int
CLKX ext
CLKX int
CLKX ext
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
(2)
MIN
2P
D–5
C–5
(3)
(3)
MAX
D+5
C+5
(3)
(3)
UNIT
ns
ns
ns
ns
ns
ns
ns
0
3
0
3
4
27
4
27
8
14
9
28
8
14
P+8
P + 14
0
6
P
P+6
8
14
P+8
P + 14
0
6
P
P+6
ns
ns
ns
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
2P = 1/CLKG in ns.
C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
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Electrical Specifications
175
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