SPRS439I – JUNE 2007 – REVISED MARCH 2011
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6.16 Multichannel Buffered Serial Port (McBSP) Timing
6.16.1 McBSP Transmit and Receive Timing
Table 6-55. McBSP Timing Requirements
(1)
NO.
McBSP module clock (CLKG, CLKX, CLKR) range
McBSP module cycle time (CLKG, CLKX, CLKR) range
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
t
c(CKRX)
t
w(CKRX)
t
r(CKRX)
t
f(CKRX)
t
su(FRH-CKRL)
t
h(CKRL-FRH)
t
su(DRV-CKRL)
t
h(CKRL-DRV)
t
su(FXH-CKXL)
t
h(CKXL-FXH)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
Fall time, CLKR/X
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
Hold time, DR valid after CLKR low
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
(1)
18
2
0
6
18
2
0
6
18
2
0
6
ns
ns
ns
ns
ns
(2)
MIN
1
MAX
25
(3)
UNIT
kHz
MHz
ns
ms
ns
ns
40
1
2P
P–7
7
7
ns
ns
ns
(2)
(3)
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
CLKSRG
(1
)
CLKGDV)
CLKSRG can be LSPCLK, CLKX,
2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG =
CLKR as source. CLKSRG
≤
(SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (25 MHz).
174
Electrical Specifications
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