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SPRS439I – JUNE 2007 – REVISED MARCH 2011
6.14.6 External Interface Write Timing
Table 6-40. External Interface Write Switching Characteristics
PARAMETER
t
d(XCOH-XZCSL)
t
d(XCOHL-XZCSH)
t
d(XCOH-XA)
t
d(XCOHL-XWEL)
t
d(XCOHL-XWEH)
t
d(XCOH-XRNWL)
t
d(XCOHL-XRNWH)
t
en(XD)XWEL
t
d(XWEL-XD)
t
h(XA)XZCSH
t
h(XD)XWE
t
dis(XD)XRNW
(1)
(2)
(3)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE0, XWE1
Delay time, XCLKOUT high to XR/W low
Delay time, XCLKOUT high/low to XR/W high
Enable time, data bus driven from XWE0, XWE1 low
Delay time, data valid after XWE0, XWE1 active low
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE0, XWE1 inactive high
Maximum time for DSP to release the data bus after XR/W inactive high
TW – 2
(2)
(3)
(1)
MIN
–1
MAX
1
0.5
1.5
2
2
1
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
low
Delay time, XCLKOUT high/low to XWE0, XWE1 high
–1
0
0.5
1
4
ns
XWE1 is used in 32-bit data bus mode only. In 16-bit mode, this signal is XA0.
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which remains high.
This includes alignment cycles.
TW = Trail period, write access. See
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Electrical Specifications
157
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