TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
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SPRS439I–JUNE 2007–REVISED MARCH 2011
Table 6-18. HALT Mode Timing Requirements
MIN NOM
MAX
UNIT
cycles
cycles
(1)
tw(WAKE-GPIO)
tw(WAKE-XRS)
(1) See Table 6-11 for an explanation of toscst
Pulse duration, GPIO wake-up signal
toscst + 2tc(OSCCLK)
Pulse duration, XRS wakeup signal
toscst + 8tc(OSCCLK)
.
Table 6-19. HALT Mode Switching Characteristics
PARAMETER
MIN
TYP
MAX
45tc(SCO)
UNIT
cycles
cycles
Delay time, IDLE instruction executed to
XCLKOUT low
td(IDLE-XCOL)
tp
32tc(SCO)
PLL lock-up time
131072 tc(OSCCLK)
Delay time, PLL lock to program execution resume
1125tc(SCO)
35tc(SCO)
cycles
cycles
•
•
Wake up from flash
Flash module in sleep state
td(WAKE-HALT)
–
Wake up from SARAM
Copyright © 2007–2011, Texas Instruments Incorporated
Electrical Specifications
137
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