SPRS439I – JUNE 2007 – REVISED MARCH 2011
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6.9.2
GPIO - Input Timing
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
t
w(SP)
t
w(IQSW)
Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Sampling Period determined
by GPxCTRL[QUALPRD]
(B)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5
(C)
)
Output From
Qualifier
A.
This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value
"n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin
will be sampled).
The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure
5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide
pulse ensures reliable recognition.
B.
C.
D.
Figure 6-10. Sampling Mode
Table 6-13. General-Purpose Input Timing Requirements
MIN
t
w(SP)
t
w(IQSW)
t
w(GPI)
(1)
(2)
(2)
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
Sampling period
Input qualifier sampling window
Pulse duration, GPIO low/high
QUALPRD = 0
QUALPRD
≠
0
Synchronous mode
With input qualifier
1t
c(SCO)
2t
c(SCO)
* QUALPRD
t
w(SP)
* (n
(1)
– 1)
2t
c(SCO)
t
w(IQSW)
+ t
w(SP)
+ 1t
c(SCO)
"n" represents the number of qualification samples as defined by GPxQSELn register.
For t
w(GPI)
, pulse width is measured from V
IL
to V
IL
for an active low signal and V
IH
to V
IH
for an active high signal.
132
Electrical Specifications
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