TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
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SPRS439I–JUNE 2007–REVISED MARCH 2011
4.12 Inter-Integrated Circuit (I2C)
The device contains one I2C Serial Port. Figure 4-17 shows how the I2C peripheral module interfaces
within the device.
System Control Block
C28x CPU
I2CAENCLK
SYSCLKOUT
SYSRS
Control
Data[16]
Data[16]
SDAA
SCLA
I2C-A
Addr[16]
I2CINT1A
I2CINT2A
GPIO
MUX
PIE
Block
A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are
also at the SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCR0 register turns off the clock to the I2C port for low power
operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 4-17. I2C Peripheral Module Interfaces
The I2C module has the following features:
•
Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
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–
–
–
–
–
–
–
Support for 1-bit to 8-bit format transfers
7-bit and 10-bit addressing modes
General call
START byte mode
Support for multiple master-transmitters and slave-receivers
Support for multiple slave-transmitters and master-receivers
Combined master transmit/receive and receive/transmit mode
Data transfer rate from 10 kbps up to 400 kbps (I2C Fast-mode rate)
•
•
One 16-word receive FIFO and one 16-word transmit FIFO
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
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–
–
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Transmit-data ready
Receive-data ready
Register-access ready
No-acknowledgment received
Copyright © 2007–2011, Texas Instruments Incorporated
Peripherals
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