TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com
SPRS439I–JUNE 2007–REVISED MARCH 2011
Figure 4-15 shows the SCI module block diagram.
SCICTL1.1
SCITXD
SCITXD
TXSHF
Register
Frame Format and Mode
Parity
TXENA
TX EMPTY
SCICTL2.6
Even/Odd
Enable
8
SCICCR.6 SCICCR.5
TX INT ENA
TXRDY
Transmitter-Data
Buffer Register
SCICTL2.7
SCICTL2.0
8
TXWAKE
TXINT
TX FIFO _0
SCICTL1.3
TX Interrupt Logic
TX FIFO _1
- - - - -
To CPU
TX
FIFO
Interrupts
1
SCI TX Interrupt Select Logic
TX FIFO _15
WUT
SCITXBUF.7-0
TX FIFO Registers
SCIFFENA
AutoBaud Detect Logic
SCIRXD
SCIFFTX.14
SCIHBAUD. 15 - 8
Baud Rate
MSbyte
Register
SCIRXD
RXSHF Register
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 - 0
RXENA
SCICTL1.0
8
Baud Rate
LSbyte
Register
SCICTL2.1
RXRDY
RX/BK INT ENA
Receive-Data
Buffer Register
SCIRXBUF.7-0
SCIRXST.6
BRKDT
8
SCIRXST.5
RX FIFO _15
- - - - -
RX
FIFO
Interrupts
RX FIFO _1
RX FIFO _0
RXINT
To CPU
RX Interrupt Logic
SCIRXBUF.7-0
RX FIFO Registers
RXFFOVF
SCIRXST.7 SCIRXST.4 - 2
SCIFFRX.15
RX Error
FE OE PE
RX Error
RX ERR INT ENA
SCI RX Interrupt Select Logic
SCICTL1.6
Figure 4-15. Serial Communications Interface (SCI) Module Block Diagram
Copyright © 2007–2011, Texas Instruments Incorporated
Peripherals
95
Submit Documentation Feedback
Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234
TMS320F28232
TI [ TEXAS INSTRUMENTS ]
