TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439I–JUNE 2007–REVISED MARCH 2011
www.ti.com
6-5
Clocking and Nomenclature (100-MHz Devices) ........................................................................... 126
6-6
Input Clock Frequency ......................................................................................................... 127
XCLKIN Timing Requirements – PLL Enabled ............................................................................. 127
XCLKIN Timing Requirements – PLL Disabled ............................................................................ 127
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ...................................................... 127
Power Management and Supervisory Circuit Solutions ................................................................... 128
Reset (XRS) Timing Requirements .......................................................................................... 130
General-Purpose Output Switching Characteristics........................................................................ 131
General-Purpose Input Timing Requirements .............................................................................. 132
IDLE Mode Timing Requirements ........................................................................................... 134
IDLE Mode Switching Characteristics ....................................................................................... 134
STANDBY Mode Timing Requirements ..................................................................................... 135
STANDBY Mode Switching Characteristics ................................................................................ 135
HALT Mode Timing Requirements ........................................................................................... 137
HALT Mode Switching Characteristics ...................................................................................... 137
ePWM Timing Requirements ................................................................................................. 139
ePWM Switching Characteristics ............................................................................................ 139
Trip-Zone Input Timing Requirements ...................................................................................... 139
High-Resolution PWM Characteristics at SYSCLKOUT = (60 –150 MHz).............................................. 140
Enhanced Capture (eCAP) Timing Requirement .......................................................................... 140
eCAP Switching Characteristics ............................................................................................. 140
Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements .................................................. 140
eQEP Switching Characteristics ............................................................................................. 140
External ADC Start-of-Conversion Switching Characteristics............................................................. 141
External Interrupt Timing Requirements .................................................................................... 141
External Interrupt Switching Characteristics ................................................................................ 141
I2C Timing ...................................................................................................................... 142
SPI Master Mode External Timing (Clock Phase = 0) .................................................................... 143
SPI Master Mode External Timing (Clock Phase = 1) .................................................................... 145
SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 147
SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 149
Relationship Between Parameters Configured in XTIMING and Duration of Pulse ................................... 150
XINTF Clock Configurations .................................................................................................. 153
External Interface Read Timing Requirements ............................................................................. 155
External Interface Read Switching Characteristics......................................................................... 155
External Interface Write Switching Characteristics ......................................................................... 157
External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)................................... 159
External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 159
Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 159
Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)....................................... 159
External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ................................... 162
Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ....................................... 162
Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ...................................... 162
XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ...................................................... 166
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................. 167
ADC Electrical Characteristics (over recommended operating conditions) ............................................ 168
ADC Power-Up Delays......................................................................................................... 169
Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) .............................. 169
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8
List of Tables
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