TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439I–JUNE 2007–REVISED MARCH 2011
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CPU bus
INT7
ADC
CPU
ADC
PF0
External
interrupts
CPU
timers
ADC
control
and
PIE
ADC
PF2
I/F
I/F
RESULT
ADC
DMA
PF0
I/F
registers RESULT
registers
L4
SARAM
(4Kx16)
L4
I/F
CPU
L5
SARAM
(4Kx16)
McBSP A
L5
I/F
Event
triggers
DMA
6-ch
McBSP B
ePWM/
HRPWM(A)
registers
PF3
I/F
L6
SARAM
(4Kx16)
L6
I/F
L7
SARAM
(4Kx16)
L7
I/F
DMA bus
A. The ePWM/HRPWM registers must be remapped to PF3 (through bit 0 of the MAPCNF register) before they can be
accessed by the DMA. The ePWM/HRPWM connection to DMA is not present in silicon revision 0.
Figure 4-1. DMA Functional Block Diagram
66
Peripherals
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