TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com
SPRS439I–JUNE 2007–REVISED MARCH 2011
3.5 Interrupts
Figure 3-5 shows how the various interrupt sources are multiplexed.
Peripherals
(SPI, SCI, I2C, CAN, McBSP(A),
ePWM(A), eCAP, eQEP, ADC(A))
Clear
DMA
WDINT
Watchdog
Low-Power Models
WAKEINT
DMA
Sync
LPMINT
SYSCLKOUT
XINT1
XINT1
Latch
Interrupt Control
XINT1CR(15:0)
XINT1CTR(15:0)
INT1
to
INT12
GPIOXINT1SEL(4:0)
XINT2SOC
XINT2
DMA
XINT2
ADC
Latch
Interrupt Control
XINT2CR(15:0)
XINT2CTR(15:0)
C28
Core
GPIOXINT2SEL(4:0)
DMA
TINT0
CPU Timer 0
DMA
TINT2
CPU Timer 2
CPU Timer 1
INT14
INT13
TINT1
GPIO0.int
XNMI_
XINT13
GPIO
Mux
Latch
Interrupt Control
XNMICR(15:0)
XNMICTR(15:0)
NMI
GPIO31.int
1
GPIOXNMISEL(4:0)
DMA
A. DMA-accessible
Figure 3-5. External and PIE Interrupt Sources
Copyright © 2007–2011, Texas Instruments Incorporated
Functional Overview
53
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