TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439I–JUNE 2007–REVISED MARCH 2011
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Table 6-63. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
30
1
MAX
M58 tsu(DRV-CKXL)
M59 th(CKXL-DRV)
M60 tsu(FXL-CKXL)
M61 tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX low
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
16P + 10
16P
2P(1)
(1) 2P = 1/CLKG
Table 6-64. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)(1)
MASTER(2)
MIN
SLAVE
MIN
NO.
PARAMETER
UNIT
MAX
MAX
M53
M54
M56
th(CKXH-FXL)
td(FXL-CKXL)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
P
2P(1)
ns
ns
ns
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last
data bit from CLKX high
P + 6
7P + 6
4P + 6
M57
td(FXL-DXV)
Delay time, FSX low to DX valid
6
ns
(1) 2P = 1/CLKG
(2) C = CLKX low pulse width = P
D = CLKX high pulse width = P
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency
is LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
M61
M60
MSB
M54
LSB
CLKX
FSX
DX
M53
M56
M55
M57
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M58
M59
(n-2)
DR
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 6-40. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
180
Electrical Specifications
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