TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
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SPRS439I–JUNE 2007–REVISED MARCH 2011
WS (Async)
Active
(A) (B)
Lead
Trail
(C)
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0, XZCS6, XZCS7
t
t
t
d(XCOH-XZCSL)
d(XCOHL-XZCSH)
d(XCOH-XA)
XA[0:19]
XRD
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
t
su(XD)XRD
(D)
XWE0, XWE1
t
a(XRD)
XR/W
t
a(A)
t
h(XD)XRD
DIN
XD[0:31], XD[0:15]
t
su(XRDYasynchL)XCOHL
t
e(XRDYasynchH)
t
h(XRDYasynchH)XZCSH
t
h(XRDYasynchL)
t
su(XRDYasynchH)XCOHL
XREADY(Asynch)
(E)
(F)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D. XWE1 is valid only in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
E. For each sample, setup time from the beginning of the access can be calculated as:
E = (XRDLEAD + XRDACTIVE -3 +n) tc(XTIM) – tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and
so forth.
F. Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE –2) tc(XTIM)
Figure 6-26. Example Read With Asynchronous XREADY Access
XTIMING register parameters used for this example :
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥ 1
3
≥ 1
1
0
N/A(1)
N/A(1)
N/A(1)
1 = XREADY
(Async)
(1) N/A = “Don’t care” for this example
Copyright © 2007–2011, Texas Instruments Incorporated
Electrical Specifications
161
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