TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
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SPRS439I–JUNE 2007–REVISED MARCH 2011
6.14.7 External Interface Ready-on-Read Timing With One External Wait State
Table 6-41. External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
PARAMETER
MIN
MAX
1
UNIT
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
–1
0.5
1.5
0.5
0.5
ns
ns
td(XCOHL-XRDL)
td(XCOHL-XRDH)
th(XA)XZCSH
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
ns
– 1.5
ns
(1)
ns
(1)
th(XA)XRD
ns
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus, except XA0, which remains high. This
includes alignment cycles.
Table 6-42. External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
MAX
UNIT
ns
(1)
ta(A)
Access time, read data from address valid
(LR + AR) – 16
(1)
ta(XRD)
Access time, read data valid from XRD active low
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
AR – 14
ns
tsu(XD)XRD
th(XD)XRD
14
0
ns
ns
(1) LR = Lead period, read access. AR = Active period, read access. See Table 6-36.
Table 6-43. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)(1)
MIN
12
6
MAX
UNIT
ns
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
ns
te(XRDYsynchH)
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
3
ns
tsu(XRDYsynchH)XCOHL
th(XRDYsynchH)XZCSH
Setup time, XREADY (synchronous) high before XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone chip select high
12
0
ns
ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 6-25:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is found to be high, then the access will finish. If XREADY (synchronous) is found to be
low, it is sampled again each tc(XTIM) until it is found to be high.
For each sample (n) the setup time (F) with respect to the beginning of the access can be calculated as:
F = (XRDLEAD + XRDACTIVE +n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-44. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
11
6
MAX
UNIT
ns
tsu(XRDYAsynchL)XCOHL
th(XRDYAsynchL)
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
ns
te(XRDYAsynchH)
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
3
ns
tsu(XRDYAsynchH)XCOHL
th(XRDYasynchH)XZCSH
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone chip select high
11
0
ns
ns
Copyright © 2007–2011, Texas Instruments Incorporated
Electrical Specifications
159
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