TMS320VC5416
Fixed-Point Digital Signal Processor
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SPRS095O–MARCH 1999–REVISED JANUARY 2005
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3-12. Pin Control Register (PCR)
The selection of sample rate input clock is made by the combination of the CLKSM (bit 13 in SRGR2) bit
value and the SCLKME bit value as shown in Table 3-7.
Table 3-7. Sample Rate Input Clock Selection
SCLKME
CLKSM
SAMPLE RATE CLOCK MODE
0
0
1
1
0
1
0
1
Reserved (CLKS pin unavailable)
CPU clock
BCLKR
BCLKX
When the SCLKME bit is cleared to 0, the CLKSM bit is used, as before, to select either the CPU clock or
the CLKS pin (not bonded out on the device package) as the sample rate input clock. Setting the
SCLKME bit to 1 enables the CLKSM bit to select between the BCLKR pin or BCLKX pin for the sample
rate input clock.
When either the BCLKR or CLKX is configured this way, the output buffer for the selected pin is
automatically disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKR pin is configured as
the input of the sample rate generator. Both the transmitter and receiver circuits can be synchronized to
the sample rate generator output by setting the CLKXM and CLKRM bits of the pin configuration register
(PCR) to 1. Note that the sample rate generator output will only be driven on the BCLKX pin since the
BCLKR output buffer is automatically disabled.
The McBSP is fully static and operates at arbitrary low clock frequencies. For maximum operating
frequency, see Section 5.5.10.
3.9 Hardware Timer
The device features a 16-bit timing circuit with a 4-bit prescaler. The timer counter is decremented by one
every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timer
can be stopped, restarted, reset, or disabled by specific status bits.
3.10 Clock Generator
The clock generator provides clocks to the device, and consists of a phase-locked loop (PLL) circuit. The
clock generator requires a reference clock input, which can be provided from an external clock source.
The reference clock input is then divided by two (DIV mode) to generate clocks for the device, or the PLL
circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency
by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The PLL is
an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the
input signal. Once the PLL is locked, it continues to track and maintain synchronization with the input
signal. Then, other internal clock circuitry allows the synthesis of new clock frequencies for use as master
clock for the device.
32
Functional Overview
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