TMS320VC5416
Fixed-Point Digital Signal Processor
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SPRS095O–MARCH 1999–REVISED JANUARY 2005
3.11 Enhanced External Parallel Interface (XIO2)
The device external interface has been redesigned to include several improvements, including:
simplification of the bus sequence, more immunity to bus contention when transitioning between read and
write operations, the ability for external memory access to the DMA controller, and optimization of the
power-down modes.
The bus sequence on the device still maintains all of the same interface signals as on previous 54x
devices, but the signal sequence has been simplified. Most external accesses now require 3 cycles
composed of a leading cycle, an active (read or write) cycle, and a trailing cycle. The leading and trailing
cycles provide additional immunity against bus contention when switching between read operations and
write operations. To maintain high-speed read access, a consecutive read mode that performs
single-cycle reads as on previous 54x devices is available.
Figure 3-13 shows the bus sequence for three cases: all I/O reads, memory reads in nonconsecutive
mode, or single memory reads in consecutive mode. The accesses shown in Figure 3-13 always require 3
CLKOUT cycles to complete.
CLKOUT
A[22:0]
D[15:0]
R/W
READ
MSTRB or IOSTRB
PS/DS/IS
Leading
Cycle
Read
Cycle
Trailing
Cycle
Figure 3-13. Nonconsecutive Memory Read and I/O Read Bus Sequence
Figure 3-14 shows the bus sequence for repeated memory reads in consecutive mode. The accesses
shown in Figure 3-14 require (2 + n) CLKOUT cycles to complete, where n is the number of consecutive
reads performed.
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Functional Overview
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