TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
5.5.7 Reset, BIO, Interrupt, and MP/MC Timings
Table 5-17 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 5-15,
Figure 5-16, and Figure 5-17).
Table 5-17. Reset, BIO, Interrupt, and MP/MC Timing Requirements
5416-120
5416-160
UNIT
MIN
MAX
th(RS)
Hold time, RS after CLKOUT low(1)
Hold time, BIO after CLKOUT low(1)
Hold time, INTn, NMI, after CLKOUT low(1)(2)
Hold time, MP/MC after CLKOUT low(1)
Pulse duration, RS low(3)(4)
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
th(BIO)
4
th(INT)
0
th(MPMC)
tw(RSL)
4
4H + 3
tw(BIO)S
tw(BIO)A
tw(INTH)S
tw(INTH)A
tw(INTL)S
tw(INTL)A
tw(INTL)WKP
tsu(RS)
Pulse duration, BIO low, synchronous
2H + 3
Pulse duration, BIO low, asynchronous
Pulse duration, INTn, NMI high (synchronous)
Pulse duration, INTn, NMI high (asynchronous)
Pulse duration, INTn, NMI low (synchronous)
Pulse duration, INTn, NMI low (asynchronous)
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
Setup time, RS before X2/CLKIN low(2)(1)
Setup time, BIO before CLKOUT low(1)
Setup time, INTn, NMI, RS before CLKOUT low(1)
Setup time, MP/MC before CLKOUT low(1)
4H
2H + 2
4H
2H + 2
4H
7
3
tsu(BIO)
7
tsu(INT)
7
tsu(MPMC)
5
(1) These inputs can be driven from an asynchronous source, therefore, there are no specific timing requirements with respect to CLKOUT,
however, if setup and hod timings are met, the input will be recognized on the CLKOUT edge referenced.
(2) The external interrupts (INT0-INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer that samples thse
inputs with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a1-0-0 sequence at the timing
that is corresponding to three CLKOUTs sampling sequence.
(3) If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure
synchronization and lock-in of the PLL.
(4) Note that RS may cause a change in clock frequency, therefore changing the value of H.
X2/CLKIN
t
su(RS)
t
w(RSL)
RS, INTn, NMI
CLKOUT
BIO
t
su(INT)
t
h(RS)
t
su(BIO)
t
h(BIO)
t
w(BIO)S
Figure 5-15. Reset and BIO Timings
74
Electrical Specifications
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