TMS320VC5416
Fixed-Point Digital Signal Processor
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SPRS095O–MARCH 1999–REVISED JANUARY 2005
5.5.6 HOLD and HOLDA Timings
Table 5-15 and Table 5-16 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5-14).
Table 5-15. HOLD and HOLDA Timing Requirements
5416-120
5416-160
UNIT
MIN
4H+8
7
MAX
tw(HOLD)
tsu(HOLD)
Pulse duration, HOLD low duration
Setup time, HOLD before CLKOUT low(1)
ns
ns
(1) This input can be driven from an asynchronous source, therefore, there are no specific timing requirments with respect to CLKOUT.
However, if this timing is met, the input will be recognized on the CLKOUT edge referenced.
Table 5-16. HOLD and HOLDA Switching Characteristics
5416-120
5416-160
PARAMETER
UNIT
MIN
MAX
tdis(CLKL-A)
tdis(CLKL-RW)
tdis(CLKL-S)
ten(CLKL-A)
ten(CLKL-RW)
ten(CLKL-S)
Disable time, Address, PS, DS, IS high impedance from CLKOUT low
Disable time, R/W high impedance from CLKOUT low
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
Enable time, Address, PS, DS, IS valid from CLKOUT low
Enable time, R/W enabled from CLKOUT low
3
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
2H+3
2H+3
2H+3
4
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
Valid time, HOLDA low after CLKOUT low
2
– 1
tv(HOLDA)
tw(HOLDA)
Valid time, HOLDA high after CLKOUT low
– 1
4
Pulse duration, HOLDA low duration
2H–3
72
Electrical Specifications
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