T M S3 2 0 VC5 402
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multiply-by-N clock option
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate
the internal machine cycle. The selection of the clock mode and the value of N is described in the clock generator
section.
When an external clock source is used, the external frequency injected must conform to specifications listed
in the timing requirements table.
NOTE:All revisions of the ’5402 can be operated with an external clock source, provided that the proper
voltage levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to
the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to the recommended
operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
†
timing requirements (see Figure 12)
MIN
MAX
200
100
50
UNIT
‡
20
‡
20
‡
20
Integer PLL multiplier N (N = 1–15)
PLL multiplier N = x.5
t
Cycle time, X2/CLKIN
ns
c(CI)
PLL multiplier N = x.25, x.75
t
t
Fall time, X2/CLKIN
Rise time, X2/CLKIN
8
8
ns
ns
f(CI)
r(CI)
†
‡
N = Multiplication factor
The multiplication factor and minimum X2/CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within the specified
range (tc(CO))
switching characteristics over recommended operating conditions [H = 0.5t
(see Figure 10 and Figure 12)
]
c(CO)
PARAMETER
MIN
10
4
TYP
MAX
UNIT
ns
†
t
Cycle time, CLKOUT
t
c(CO)
c(CI)/N
10
t
Delay time, X2/CLKIN high/low to CLKOUT high/low
Fall time, CLKOUT
17
ns
d(CI-CO)
t
2
2
ns
f(CO)
r(CO)
w(COL)
w(COH)
p
t
t
t
t
Rise time, CLKOUT
ns
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
Transitory phase, PLL lock up time
H–2
H–2
H
H
ns
ns
30
ms
†
N = Multiplication factor
t
f(CI)
t
r(CI)
t
c(CI)
X2/CLKIN
t
d(CI-CO)
t
f(CO)
t
w(COH)
t
c(CO)
t
w(COL)
t
tp
r(CO)
Unstable
CLKOUT
Figure 12. External Multiply-by-One Clock Timing
38
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