欢迎访问ic37.com |
会员登录 免费注册
发布采购

TMS320VC5402PGE100 参数 Datasheet PDF下载

TMS320VC5402PGE100图片预览
型号: TMS320VC5402PGE100
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [FIXED-POINT DIGITAL SIGNAL PROCESSOR]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器时钟
文件页数/大小: 68 页 / 939 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号TMS320VC5402PGE100的Datasheet PDF文件第33页浏览型号TMS320VC5402PGE100的Datasheet PDF文件第34页浏览型号TMS320VC5402PGE100的Datasheet PDF文件第35页浏览型号TMS320VC5402PGE100的Datasheet PDF文件第36页浏览型号TMS320VC5402PGE100的Datasheet PDF文件第38页浏览型号TMS320VC5402PGE100的Datasheet PDF文件第39页浏览型号TMS320VC5402PGE100的Datasheet PDF文件第40页浏览型号TMS320VC5402PGE100的Datasheet PDF文件第41页  
T MS 3 20 VC 54 02  
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R  
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000  
divide-by-two clock option (PLL disabled)  
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two to generate  
the internal machine cycle. The selection of the clock mode is described in the clock generator section.  
When an external clock source is used, the frequency injected must conform to specifications listed in the timing  
requirements table.  
NOTE:All revisions of the ’5402 can be operated with an external clock source, provided that the proper  
voltage levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to  
the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to the recommended  
operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.  
timing requirements (see Figure 11)  
MIN  
MAX  
UNIT  
ns  
t
t
t
Cycle time, X2/CLKIN  
Fall time, X2/CLKIN  
Rise time, X2/CLKIN  
20  
c(CI)  
f(CI)  
r(CI)  
8
8
ns  
ns  
This device utilizes a fully static design and therefore can operate with t  
approaching 0 Hz.  
approaching . The device is characterized at frequencies  
c(CI)  
switching characteristics over recommended operating conditions [H = 0.5t  
Figure 11, and the recommended operating conditions table)  
] (see Figure 10,  
c(CO)  
PARAMETER  
MIN  
TYP  
MAX  
UNIT  
ns  
10  
t
Cycle time, CLKOUT  
2t  
c(CI)  
10  
c(CO)  
t
Delay time, X2/CLKIN high to CLKOUT high/low  
Fall time, CLKOUT  
4
17  
ns  
d(CIH-CO)  
t
2
2
ns  
f(CO)  
t
t
t
Rise time, CLKOUT  
ns  
r(CO)  
Pulse duration, CLKOUT low  
Pulse duration, CLKOUT high  
H–2  
H–2  
H
H
ns  
w(COL)  
w(COH)  
ns  
This device utilizes a fully static design and therefore can operate with t  
approaching 0 Hz.  
It is recommended that the PLL clocking option be used for maximum frequency operation.  
approaching . The device is characterized at frequencies  
c(CI)  
t
r(CI)  
t
f(CI)  
t
c(CI)  
X2/CLKIN  
CLKOUT  
t
w(COH)  
t
f(CO)  
t
c(CO)  
t
r(CO)  
t
d(CIH-CO)  
t
w(COL)  
Figure 11. External Divide-by-Two Clock Timing  
37  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443