ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈꢈ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢈꢈꢊ
ꢋ ꢌꢍ ꢎꢏꢐꢑꢒ ꢌ ꢓꢀ ꢏꢌ ꢔꢌ ꢀꢕꢖ ꢂꢌ ꢔ ꢓꢕꢖ ꢑꢗ ꢒ ꢆꢎ ꢂ ꢂꢒ ꢗ ꢂ
SPRS073L − AUGUST 1998 − REVISED JUNE 2004
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 44)
−150
−167
NO.
UNIT
MIN
35
10
9
MAX
1
3
4
t
t
t
Cycle time, TCK
ns
ns
ns
c(TCK)
Setup time, TDI/TMS/TRST valid before TCK high
Hold time, TDI/TMS/TRST valid after TCK high
su(TDIV-TCKH)
h(TCKH-TDIV)
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 44)
−150
−167
NO.
PARAMETER
UNIT
MIN
MAX
2
t
Delay time, TCK low to TDO valid
–3
18
ns
d(TCKL-TDOV)
1
TCK
TDO
2
2
4
3
TDI/TMS/TRST
Figure 44. JTAG Test-Port Timing
81
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