TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
multichannel buffered serial port timing (continued)
t
t
t
c(BCKRX)
w(BCKRXH)
w(BCKRXL)
t
r(BCKRX)
BCLKR
BFSR (int)
BFSR (ext)
t
d(BCKRH–BFRV)
t
d(BCKRH–BFRV)
t
r(BCKRX)
tsu(BFRH–BCKRL)
t
h(BCKRL–BFRH)
t
h(BCKRL–BDRV)
(n–2)
t
su(BDRV–BCKRL)
t
BDR
Bit (n–1)
(n–3)
(n–4)
(n–3)
(RDATDLY=00b)
su(BDRV–BCKRL)
t
h(BCKRL–BDRV)
(n–2)
BDR
(RDATDLY=01b)
Bit (n–1)
t
t
su(BDRV–BCKRL)
h(BCKRL–BDRV)
(n–2)
BDR
(RDATDLY=10b)
Bit (n–1)
Figure 28. McBSP Receive Timings
t
t
c(BCKRX)
w(BCKRXH)
t
r(BCKRX)
t
f(BCKRX)
t
w(BCKRXL)
BCLKX
BFSX (int)
BFSX (ext)
t
d(BCKXH–BFXV)
t
d(BCKXH–BFXV)
t
su(BFXH–BCKXL)
t
h(BCKXL–BFXH)
t
d(BDFXH–BDXV)
Bit (n–1)
t
t
t
d(BCKXH–BDXV)
(n–3)
e(BDFXH–BDX)
BDX
Bit 0
(n–2)
(n–4)
(n–3)
(n–2)
(XDATDLY=00b)
d(BCKXH–BDXV)
(n–2)
t
e(BCKXH–BDX)
Bit (n–1)
BDX
(XDATDLY=01b)
Bit 0
t
d(BCKXH–BDXV)
Bit (n–1)
t
dis(BCKXH–BDXHZ)
Bit 0
t
e(BCKXH–BDX)
BDX
(XDATDLY=10b)
Figure 29. McBSP Transmit Timings
61
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443