TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
multichannel buffered serial port timing
†
timing requirements for the McBSP [H=0.5t
] (see Figure 28 and Figure 29)
c(CO)
MIN
4H
6
MAX
UNIT
ns
t
t
Cycle time, BCLKR/X
BCLKR/X ext
BCLKR/X ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKR/X ext
BCLKR/X ext
c(BCKRX)
Pulse duration, BCLKR/X or BCLKR/X high
ns
w(BCKRX)
0
t
t
t
t
t
t
Hold time, external BFSR high after BCLKR low
ns
ns
ns
ns
ns
ns
h(BCKRL-BFRH)
h(BCKRL-BDRV)
h(BCKXL-BFXH)
su(BFRH-BCKRL)
su(BDRV-BCKRL)
su(BFXH-BCKXL)
4
0
Hold time, BDR valid after BCLKR low
5
0
Hold time, external BFSX high after BCLKX low
Setup time, external BFSR high before BCLKR low
Setup time, BDR valid before BCLKR low
4
10
4
10
3
10
6
Setup time, external BFSX high before BCLKX low
t
t
Rise time, BCKR/X
Fall time, BCKR/X
8
8
ns
ns
r(BCKRX)
f(BCKRX)
†
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443