TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
multichannel buffered serial port timing (continued)
†
timing requirements for McBSP as SPI master or slave: [H=0.5t
(see Figure 32)
] CLKSTP = 11b, CLKXP = 0
c(CO)
MASTER
SLAVE
MIN MAX
UNIT
MIN
12
4
MAX
t
t
Setup time, BDR valid before BCLKX high
Hold time, BDR valid after BCLKX high
2 – 12H
5 +12H
ns
ns
su(BDRV-BCKXH)
h(BCKXH-BDRV)
t
t
Setup time, BFSX low before BCLKX high
Cycle time, BCLKX
10
ns
ns
su(BFXL-BCKXH)
12H
32H
c(BCKX)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5t
CLKXP = 0 (see Figure 32)
] CLKSTP = 11b,
c(CO)
†
‡
MASTER
SLAVE
UNIT
PARAMETER
MIN MAX
MIN
MAX
§
t
t
t
Hold time, BFSX low after BCLKX low
C – 5 C + 5
T – 5 T + 5
ns
ns
ns
h(BCKXL-BFXL)
d(BFXL-BCKXH)
d(BCKXL-BDXV)
¶
Delay time, BFSX low to BCLKX high
Delay time, BCLKX low to BDX valid
–2
12 6H + 4 10H + 19
Disabletime, BDX high impedance following last data bit from BCLKX
low
t
–2
10 6H + 4 10H + 17
ns
ns
dis(BCKXL-BDXHZ)
t
Delay time, BFSX low to BDX valid
D – 2 D +10
4H – 4
8H + 17
d(BFXL-BDXV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
§
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
¶
t
c(BCKX)
MSB
LSB
t
su(BFXL-BCKXH)
BCLKX
t
t
d(BFXL-BCKXH)
h(BCKXL-BFXL)
BFSX
t
t
t
d(BCKXL-BDXV)
d(BFXL-BDXV)
dis(BCKXL-BDXHZ)
BDX
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCKXH)
t
h(BCKXH-BDRV)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
Figure 32. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
64
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