TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
multichannel buffered serial port timing (continued)
†
switching characteristics for the McBSP [H=0.5t
] (see Figure 28 and Figure 29)
c(CO)
PARAMETER
MIN
MAX
UNIT
ns
t
t
t
t
Cycle time, BCLKR/X
BCLKR/X int
BCLKR/X int
BCLKR/X int
BCLKR int
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BFSX int
4H
c(BCKRX)
‡
‡
‡
Pulse duration, BCLKR/X high
Pulse duration, BCLKR/X low
Delay time, BCLKR high to internal BFSR valid
D–4
C–4
D+1
ns
w(BCKRXH)
w(BCKRXL)
d(BCKRH-BFRV)
‡
C+1
ns
–3
–3
2
3
8
ns
t
Delay time, BCLKX high to internal BFSX valid
ns
ns
d(BCKXH-BFXV)
15
5
–8
1
t
Disable time, BCLKX high to BDX high impedance following last data bit
dis(BCKXH-BDXHZ)
19
11
20
11
20
25
27
0
Delay time, BCLKX high to BDX valid. This applies to all bits except the first
bit transmitted.
5
t
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
ns
§
d(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid.
Only applies to first bit transmitted when in Data Delay 1
or 2 (XDATDLY=01b or 10b) modes
–4
2
§
Enable time, BCLKX high to BDX driven.
Only applies to first bit transmitted when in Data Delay 1
or 2 (XDATDLY=01b or 10b) modes
t
t
t
ns
ns
ns
e(BCKXH-BDX)
d(BFXH-BDXV)
e(BFXH-BDX)
6
12
9
12
25
26
§
Delay time, BFSX high to BDX valid.
Only applies to first bit transmitted when in Data Delay 0
(XDATDLY=00b) mode.
BFSX ext
BFSX int
BFSX ext
BFSX int
–1
2
§
Enable time, BFSX high to BDX driven.
Only applies to first bit transmitted when in Data Delay 0
(XDATDLY=00b) mode
BFSX ext
BFSX int
9
BFSX ext
13
†
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
‡
§
T=BCLKRX period = (1 + CLKGDV) * 2H
C=BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D=BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
Seethe TMS320C54xEnhancedPeripheralsReferenceSet, Volume5(literaturenumberSPRU302)foradescriptionoftheDXenable(DXENA)
and data delay features of the McBSP.
60
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