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TMS320VC5407PGER 参数 Datasheet PDF下载

TMS320VC5407PGER图片预览
型号: TMS320VC5407PGER
PDF下载: 下载PDF文件 查看货源
内容描述: [IC,DSP,16-BIT,QFP,144PIN,PLASTIC]
分类和应用:
文件页数/大小: 107 页 / 1364 K
品牌: TI [ TEXAS INSTRUMENTS ]
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Electrical Specifications
Table 5–29. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
MASTER
MIN
MAX
SLAVE
MIN
2 – 6P‡
5 + 12P‡
MAX
UNIT
ns
ns
tsu(BDRV-BCKXH) Setup time, BDR valid before BCLKX high
12
th(BCKXH-BDRV)
Hold time, BDR valid after BCLKX high
4
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ P = 0.5 * processor clock
Table 5–30. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
MASTER§
PARAMETER
th(BCKXH-BFXL)
td(BFXL-BCKXL)
td(BCKXL-BDXV)
tdis(BCKXH-BDXHZ)
tdis(BFXH-BDXHZ)
Hold time, BFSX low after BCLKX high¶
Delay time, BFSX low to BCLKX low#
Delay time, BCLKX low to BDX valid
Disable time, BDX high impedance following last data bit from
BCLKX high
Disable time, BDX high impedance following last data bit from
BFSX high
MIN
T–3
D–4
–4
D–2
MAX
T+4
D+3
5 6P + 2‡
D+3
2P – 4‡
6P + 17‡
10P + 17‡
SLAVE
MIN
MAX
UNIT
ns
ns
ns
ns
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
4P + 2‡
8P + 17‡
ns
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ P = 0.5 * processor clock
§ T = BCLKX period = (1 + CLKGDV) * 2P
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
¶ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
LSB
BCLKX
th(BCKXH-BFXL)
BFSX
tdis(BFXH-BDXHZ)
tdis(BCKXH-BDXHZ)
BDX
Bit 0
tsu(BDRV-BCKXH)
BDR
Bit 0
MSB
td(BFXL-BCKXL)
td(BFXL-BDXV)
td(BCKXL-BDXV)
Bit(n-1)
(n-2)
th(BCKXH-BDRV)
Bit(n-1)
(n-2)
(n-3)
(n-4)
(n-3)
(n-4)
Figure 5–26. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
86
SPRS007B
November 2001 – Revised July 2003