Functional Overview
3.6
On-Chip Peripherals
The 5407/5404 device has the following peripherals:
•
•
•
•
•
•
•
•
•
Software-programmable wait-state generator
Programmable bank-switching
A host-port interface (HPI8/16)
Three multichannel buffered serial ports (McBSPs)
Two hardware timers
A clock generator with a multiple phase-locked loop (PLL)
Enhanced external parallel interface (XIO2)
A DMA controller (DMA)
A UART with an integrated baud rate generator
3.6.1 Software-Programmable Wait-State Generator
The software wait-state generator of the 5407/5404 can extend external bus cycles by up to fourteen machine
cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line.
When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator
are automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of
the 5407/5404.
The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs
of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five
separate address ranges. This allows a different number of wait states for each of the five address ranges.
Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)
defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is
initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown
in Figure 3–7 and described in Table 3–3.
15
XPA
R/W-0
14
I/O
R/W-111
12
11
DATA
R/W-111
9
8
DATA
6
DATA
R/W-111
5
PROGRAM
R/W-111
3
2
PROGRAM
R/W-111
0
LEGEND:
R = Read, W = Write,
n = value after reset
Figure 3–7. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
18
SPRS007B
November 2001 – Revised July 2003
TI [ TEXAS INSTRUMENTS ]
