Functional Overview
The standard on-chip ROM layout is shown in Table 3–1.
Table 3–1. Standard On-Chip ROM Layout
†
ADDRESS RANGE
C000h–D4FFh
D500h–F7FFh
F800h–FBFFh
FC00h–FCFFh
FD00h–FDFFh
FE00h–FEFFh
FF00h–FF7Fh
Reserved
Bootloader
µ-Law
expansion table
A-Law expansion table
Sine look-up table
Reserved†
DESCRIPTION
ROM tables for the GSM EFR speech codec
FF80h–FFFFh
Interrupt vector table
† In the 5407/5404 ROM, 128 words are reserved for factory device-testing purposes. Application
code to be implemented in on-chip ROM must reserve these 128 words at addresses
FF00h–FF7Fh in program space.
3.3
On-Chip RAM
The 5407 device contains 40K-words
×
16-bit of on-chip dual-access RAM (DARAM), while the 5404 device
contains 16K-words x 16-bit of DARAM.
The DARAM is composed of five blocks of 8K words each. Each block in the DARAM can support two reads
in one cycle, or a read and a write in one cycle. The five blocks of DARAM on the 5407 are located in the
address range 0080h–9FFFh in data space, and can be mapped into program/data space by setting the OVLY
bit to one.
On the 5404, the two blocks of DARAM are located at 0080h–3FFFh in data space and can also be mapped
into data space by setting OVLY to one.
3.4
On-Chip Memory Security
The 5407/5404 device provides maskable options to protect the contents of on-chip memories. When the
ROM protect option is selected, no externally originating instruction can access the on-chip ROM; when the
RAM protect option is selected, HPI RAM is protected; HPI writes are not restricted, but HPI reads are
restricted to 2000h – 3FFFh.
November 2001 – Revised July 2003
SPRS007B
13
TI [ TEXAS INSTRUMENTS ]
