Functional Overview
3
Functional Overview
The following functional overview is based on the block diagram in Figure 3–1.
P, C, D, E Buses and Control Signals
Cbus
Dbus
Cbus
Pbus
Dbus
Pbus
Ebus
Ebus
Pbus
128K Program
ROM
‡
MBus
GPIO
TI BUS
RHEA
Bridge
RHEA Bus
McBSP0
McBSP1
RHEA bus
MBus
McBSP2
MBus
UART
TIMER
APLL
Clocks
JTAG
54X cLEAD
40K RAM
Dual Access
Program/Data
†
XIO
Enhanced XIO
16HPI
16 HPI
xDMA
logic
RHEAbus
† 16K for 5404
‡ 64K for 5404
Figure 3–1. TMS320VC5407/TMS320VC5404 Functional Block Diagram
3.1
Memory
The 5407/5404 device provides both on-chip ROM and RAM memories to aid in system performance and
integration.
3.1.1 Data Memory
The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the on-chip
RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device
automatically generates an external access.
The advantages of operating from on-chip memory are as follows:
•
•
•
•
Higher performance because no wait states are required
Higher performance because of better flow within the pipeline of the central arithmetic logic unit (CALU)
Lower cost than external memory
Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
November 2001 – Revised July 2003
SPRS007B
11
TI [ TEXAS INSTRUMENTS ]
