Electrical Specifications
Table 5–36. HPI16 Mode Switching Characteristics
PARAMETER
MIN
MAX
UNIT
t
Delay time, DS low to HD driven
0
10
ns
d(DSL-HDD)
Case 1a: Memory accesses initiated immediately following a write
when DMAC is active in 16-bit mode and t was < 18H
32P+20 – t
w(DSH)
w(DSH)
w(DSH)
w(DSH)
Case 1b: Memory accesses not immediately following a write when
DMAC is active in 16-bit mode
16P + 20
Delay time,
DS low to HD
valid for first
word of an
HPI read
Case 1c: Memory accesses initiated immediately following a write
48P+20 – t
when DMAC is active in 32-bit mode and t
w(DSH)
was < 26H
t
ns
d(DSL-HDV1)
Case 1d: Memory access not immediately following a write when
DMAC is active in 32-bit mode
24P + 20
Case 2a: Memory accesses initiated immediately following a write
20P+20 – t
10P + 20
when DMAC is inactive and t
w(DSH)
was < 10H
Case 2b: Memory accesses not immediately following a write when
DMAC is inactive
Memory writes when no DMA is active
10P + 5
16P + 5
24P + 5
7
Delay
DS high to
HRDY high
time,
Memory writes with one or more 16-bit DMA channels active
Memory writes with one or more 32-bit DMA channels active
t
ns
d(DSH-HYH)
ns
ns
ns
ns
ns
t
Valid time, HD valid after HRDY high
Hold time, HD valid after DS rising edge, read
Delay time, CLKOUT rising edge to HRDY high
Delay time, DS low to HRDY low
v(HYH-HDV)
t
1
6
5
h(DSH-HDV)R
t
d(COH-HYH)
t
12
12
d(DSL-HYL)
t
Delay time, DS high to HRDY low
d(DSH–HYL)
HCS
t
w(DSH)
t
c(DSH–DSH)
HDS
t
t
su(HBV–DSL)
w(DSL)
t
su(HBV–DSL)
h(DSL–HBV)
t
t
h(DSL–HBV)
HR/W
t
su(HAV–DSL)
t
h(DSH–HAV)
HA[17:0]
Valid Address
Valid Address
t
h(DSH–HDV)R
t
d(DSL–HDV1)
t
t
h(DSH–HDV)R
d(DSL–HDV1)
Data
HD[15:0]
HRDY
Data
t
d(DSL–HDD)
t
d(DSL–HDD)
t
v(HYH–HDV)
t
v(HYH–HDV)
t
t
d(DSL–HYL)
d(DSL–HYL)
Figure 5–32. Nonmultiplexed Read Timings
93
November 2001 – Revised July 2003
SPRS007B
TI [ TEXAS INSTRUMENTS ]
