Electrical Specifications
5.15.2
HPI16 Mode
Table 5–35 and Table 5–36 assume testing over recommended operating conditions and P = 0.5 * processor
clock (see Figure 5–32 through Figure 5–34). In the following tables, DS refers to the logical OR of HCS,
HDS1, and HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These timings are
shown assuming that HDS is the signal controlling the transfer. See the
TMS320C54x DSP Reference Set,
Volume 5: Enhanced Peripherals
(literature number SPRU302) for additional information.
Table 5–35. HPI16 Mode Timing Requirements
MIN
tsu(HBV-DSL)
th(DSL-HBV)
tsu(HAV-DSH)
tsu(HAV-DSL)
th(DSH-HAV)
tw(DSL)
tw(DSH)
Setup time, HR/W valid before DS falling edge
Hold time, HR/W valid after DS falling edge
Setup time, address valid before DS rising edge (write)
Setup time, address valid before DS falling edge (read)
Hold time, address valid after DS rising edge
Pulse duration, DS low
Pulse duration, DS high
Reads
Memory accesses with no DMA activity
activity.
tc(DSH-DSH)
Cycle time, DS rising edge to
Memory accesses with 16-bit DMA activity.
16 bit
activity
next DS rising edge
Memory accesses with 32-bit DMA activity.
32 bit
activity
tsu(HDV-DSH)W
th(DSH-HDV)W
Setup time, HD valid before DS rising edge
Hold time, HD valid after DS rising edge, write
Writes
Reads
Writes
Reads
Writes
6
5
5
–(4P – 6)
1
30
10
10P + 30
10P + 10
16P + 30
16P + 10
24P + 30
24P + 10
8
2
ns
ns
ns
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
92
SPRS007B
November 2001 – Revised July 2003
TI [ TEXAS INSTRUMENTS ]
