TMS320VC5402
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multichannel buffered serial port timing
timing requirements for McBSP [H=0.5t
c(CO)
]
†
(see Figure 28 and Figure 29)
MIN
tc(BCKRX)
tw(BCKRX)
tsu(BFRH-BCKRL)
th(BCKRL-BFRH)
tsu(BDRV-BCKRL)
th(BCKRL-BDRV)
tsu(BFXH-BCKXL)
th(BCKXL-BFXH)
Cycle time, BCLKR/X
Pulse duration, BCLKR/X high or BCLKR/X low
Setup time external BFSR high before BCLKR low
time,
Hold time external BFSR high after BCLKR low
time,
Setup time BDR valid before BCLKR low
time,
Hold time BDR valid after BCLKR low
time,
Setup time external BFSX high before BCLKX low
time,
Hold time external BFSX high after BCLKX low
time,
BCLKR/X ext
BCLKR/X ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
4H
2H–2
8
1
0
3
5
0
0
4
7
0
0
3
ns
ns
ns
ns
ns
ns
MAX
UNIT
ns
ns
tr(BCKRX)
Rise time, BCKR/X
BCLKR/X ext
8
ns
tf(BCKRX)
Fall time, BCKR/X
BCLKR/X ext
8
ns
† CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
switching characteristics for McBSP [H=0.5t
c(CO)
]
†
(see Figure 28 and Figure 29)
PARAMETER
tc(BCKRX)
tw(BCKRXH)
tw(BCKRXL)
td(BCKRH-BFRV)
td(BCKXH-BFXV)
Cycle time, BCLKR/X
Pulse duration, BCLKR/X high
Pulse duration, BCLKR/X low
Delay time BCLKR high to internal BFSR valid
time,
Delay time BCLKX high to internal BFSX valid
time,
BCLKR/X int
BCLKR/X int
BCLKR/X int
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BFSX int
BFSX ext
MIN
4H
D – 2‡
C – 2‡
–2
3
0
8
–1
3
0¶
3
–1¶
3
MAX
D + 2‡
C + 2‡
2
9
4
11
4
9
7
11
3
ns
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
13
ns
ns
ns
UNIT
ns
ns
ns
ns
ns
Disable time, BCLKX high to BDX high im edance following last data
impedance
tdis(BCKXH-BDXHZ)
bit of transfer
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid
time
Delay time, BFSX high to BDX valid
td(BFXH-BDXV)
DXENA = 0§
† CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡ T = BCLKRX period = (1 + CLKGDV) * 2H
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ The transmit delay enable (DXENA) and A–bis mode (ABIS) features of the McBSP are not implemented on the TMS320VC5402.
¶ Minimum delay times also represent minimum output hold times.
54
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251–1443
TI [ TEXAS INSTRUMENTS ]
