TMS320VC5402
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
reset, BIO, interrupt, and MP/MC timings
timing requirements for reset, BIO, interrupt, and MP/MC [H = 0.5 t
c(CO)
] (see Figure 22, Figure 23,
and Figure 24)
MIN
th(RS)
th(BIO)
th(INT)
th(MPMC)
tw(RSL)
tw(BIO)S
tw(BIO)A
tw(INTH)S
tw(INTH)A
tw(INTL)S
tw(INTL)A
tw(INTL)WKP
tsu(RS)
tsu(BIO)
Hold time, RS after CLKOUT low
Hold time, BIO after CLKOUT low
Hold time, INTn, NMI, after CLKOUT low†
Hold time, MP/MC after CLKOUT low
Pulse duration, RS low‡§
Pulse duration, BIO low, synchronous
Pulse duration, BIO low, asynchronous
Pulse duration, INTn, NMI high (synchronous)
Pulse duration, INTn, NMI high (asynchronous)
Pulse duration, INTn, NMI low (synchronous)
Pulse duration, INTn, NMI low (asynchronous)
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
Setup time, RS before X2/CLKIN low¶
Setup time, BIO before CLKOUT low
0
0
0
0
4H+5
2H+2
4H
2H
4H
2H+2
4H
10
5
7
10
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu(INT)
Setup time, INTn, NMI, RS before CLKOUT low
7
10
ns
tsu(MPMC)
Setup time, MP/MC before CLKOUT low
5
ns
† The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is
corresponding to three CLKOUT sampling sequences.
‡ If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50
µs
to ensure
synchronization and lock-in of the PLL.
§ Note that RS may cause a change in clock frequency, therefore changing the value of H.
¶ Divide-by-two mode
50
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251–1443
TI [ TEXAS INSTRUMENTS ]
