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TMS320F28232PTPQ 参数 Datasheet PDF下载

TMS320F28232PTPQ图片预览
型号: TMS320F28232PTPQ
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号控制器(DSC ) [Digital Signal Controllers (DSCs)]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置时钟
文件页数/大小: 199 页 / 2655 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F28335, TMS320F28334, TMS320F28332  
TMS320F28235, TMS320F28234, TMS320F28232  
www.ti.com  
SPRS439M JUNE 2007REVISED AUGUST 2012  
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the  
following conditions:  
Transmit-data ready  
Receive-data ready  
Register-access ready  
No-acknowledgment received  
Arbitration lost  
Stop condition detected  
Addressed as slave  
An additional interrupt that can be used by the CPU when in FIFO mode  
Module-enable and module-disable capability  
Free data format mode  
The registers in Table 4-14 configure and control the I2C port operation.  
Table 4-14. I2C-A Registers  
NAME  
I2COAR  
I2CIER  
ADDRESS  
0x7900  
0x7901  
0x7902  
0x7903  
0x7904  
0x7905  
0x7906  
0x7907  
0x7908  
0x7909  
0x790A  
0x790C  
0x7920  
0x7921  
DESCRIPTION  
I2C own address register  
I2C interrupt enable register  
I2C status register  
I2CSTR  
I2CCLKL  
I2CCLKH  
I2CCNT  
I2CDRR  
I2CSAR  
I2CDXR  
I2CMDR  
I2CISRC  
I2CPSC  
I2CFFTX  
I2CFFRX  
I2CRSR  
I2CXSR  
I2C clock low-time divider register  
I2C clock high-time divider register  
I2C data count register  
I2C data receive register  
I2C slave address register  
I2C data transmit register  
I2C mode register  
I2C interrupt source register  
I2C prescaler register  
I2C FIFO transmit register  
I2C FIFO receive register  
I2C receive shift register (not accessible to the CPU)  
I2C transmit shift register (not accessible to the CPU)  
4.13 GPIO MUX  
On the 2833x/2823x devices, the GPIO MUX can multiplex up to three independent peripheral signals on  
a single GPIO pin in addition to providing individual pin bit-banging I/O capability. The GPIO MUX block  
diagram per pin is shown in Figure 4-18. Because of the open drain capabilities of the I2C pins, the GPIO  
MUX block diagram for these pins differ. See the TMS320x2833x, 2823x System Control and Interrupts  
Reference Guide (literature number SPRUFB0 ) for details.  
NOTE  
There is a 2-SYSCLKOUT cycle delay from when the write to the GPxMUXn and GPxQSELn  
registers occurs to when the action is valid.  
Copyright © 2007–2012, Texas Instruments Incorporated  
Peripherals  
99  
Submit Documentation Feedback  
Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234  
TMS320F28232  
 
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