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TMS320F28232PTPQ 参数 Datasheet PDF下载

TMS320F28232PTPQ图片预览
型号: TMS320F28232PTPQ
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号控制器(DSC ) [Digital Signal Controllers (DSCs)]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置时钟
文件页数/大小: 199 页 / 2655 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F28335, TMS320F28334, TMS320F28332  
TMS320F28235, TMS320F28234, TMS320F28232  
www.ti.com  
SPRS439M JUNE 2007REVISED AUGUST 2012  
Figure 4-16 is a block diagram of the SPI in slave mode.  
SPIFFENA  
Overrun  
INT ENA  
Receiver  
Overrun Flag  
SPIFFTX.14  
RX FIFO registers  
SPIRXBUF  
SPISTS.7  
SPICTL.4  
RX FIFO _0  
RX FIFO _1  
SPIINT/SPIRXINT  
RX FIFO Interrupt  
−−−−−  
RX FIFO _15  
RX Interrupt  
Logic  
16  
SPIRXBUF  
Buffer Register  
SPIFFOVF FLAG  
SPIFFRX.15  
To CPU  
TX FIFO registers  
SPITXBUF  
TX FIFO _15  
TX Interrupt  
Logic  
TX FIFO Interrupt  
−−−−−  
TX FIFO _1  
SPITXINT  
TX FIFO _0  
16  
SPI INT  
ENA  
SPI INT FLAG  
SPISTS.6  
SPITXBUF  
Buffer Register  
16  
SPICTL.0  
16  
M
S
M
SPIDAT  
Data Register  
S
SW1  
SW2  
SPISIMO  
SPISOMI  
M
S
M
SPIDAT.15 − 0  
S
Talk  
SPICTL.1  
(A)  
SPISTE  
State Control  
Master/Slave  
SPICTL.2  
SPI Char  
SPICCR.3 − 0  
S
3
2
1
0
SW3  
Clock  
Polarity  
Clock  
Phase  
M
S
SPI Bit Rate  
LSPCLK  
SPICCR.6  
SPICTL.3  
SPICLK  
SPIBRR.6 − 0  
M
6
5
4
3
2
1
0
A. SPISTE is driven low by the master for a slave device.  
Figure 4-16. SPI Module Block Diagram (Slave Mode)  
Copyright © 2007–2012, Texas Instruments Incorporated  
Peripherals  
97  
Submit Documentation Feedback  
Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234  
TMS320F28232  
 
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